How Many Total Registers In Armv7

The corporeality of registers depends on the ARM version. According to the ARM Reference Manual, there are thirty full general-purpose 32-bit registers, with the exception of ARMv6-M and ARMv7-1000 based processors. The first 16 registers are attainable in user-level mode, the additional registers are available in privileged software execution (with the exception of ARMv6-M and ARMv7-Grand). In this tutorial series we will work with the registers that are attainable in any privilege mode: r0-15. These 16 registers can be split into two groups: full general purpose and special purpose registers.

#	Allonym	Purpose
R0	–	General purpose
R1	–	General purpose
R2	–	Full general purpose
R3	–	General purpose
R4	–	General purpose
R5	–	General purpose
R6	–	General purpose
R7	–	Holds Syscall Number
R8	–	General purpose
R9	–	Full general purpose
R10	–	General purpose
R11	FP	Frame Arrow
Special Purpose Registers
R12	IP	Intra Procedural Call
R13	SP	Stack Pointer
R14	LR	Link Annals
R15	PC	Program Counter
CPSR	–	Current Program Status Register

The following tabular array is just a quick glimpse into how the ARM registers could relate to those in Intel processors.

ARM	Clarification	x86
R0	General Purpose	EAX
R1-R5	General Purpose	EBX, ECX, EDX, ESI, EDI
R6-R10	Full general Purpose	–
R11 (FP)	Frame Pointer	EBP
R12	Intra Procedural Telephone call	–
R13 (SP)	Stack Pointer	ESP
R14 (LR)	Link Register	–
R15 (PC)	<- Plan Counter / Instruction Arrow ->	EIP
CPSR	Current Plan State Annals/Flags	EFLAGS

R0-R12: can be used during common operations to store temporary values, pointers (locations to memory), etc. R0, for example, can be referred equally accumulator during the arithmetic operations or for storing the result of a previously called function. R7 becomes useful while working with syscalls as it stores the syscall number and R11 helps us to keep track of boundaries on the stack serving as the frame arrow (will be covered later). Moreover, the function calling convention on ARM specifies that the showtime four arguments of a office are stored in the registers r0-r3.

R13: SP (Stack Pointer). The Stack Pointer points to the top of the stack. The stack is an expanse of retentivity used for function-specific storage, which is reclaimed when the office returns. The stack arrow is therefore used for allocating infinite on the stack, by subtracting the value (in bytes) we want to allocate from the stack pointer. In other words, if we want to allocate a 32 bit value, we subtract iv from the stack arrow.

R14: LR (Link Annals). When a office call is made, the Link Annals gets updated with a retentivity address referencing the next didactics where the role was initiated from. Doing this allows the programme render to the "parent" function that initiated the "child" function call after the "child" function is finished.

R15: PC (Program Counter). The Program Counter is automatically incremented by the size of the instruction executed. This size is e'er four bytes in ARM state and two bytes in THUMB fashion. When a branch instruction is being executed, the PC holds the destination address. During execution, PC stores the address of the current instruction plus 8 (two ARM instructions) in ARM state, and the current instruction plus four (two Pollex instructions) in Thumb(v1) country. This is unlike from x86 where PC always points to the next instruction to be executed.

Let's look at how PC behaves in a debugger. We utilize the following program to store the address of pc into r0 and include two random instructions. Let'south see what happens.

.section .text .global _start  _start:  mov r0, pc  mov r1, #two  add r2, r1, r1  bkpt

In GDB nosotros set a breakpoint at _start and run it:

                      gef>                    br _start Breakpoint 1 at 0x8054                      global environment facility>                    run

Here is a screenshot of the output nosotros see first:

$r0 0x00000000   $r1 0x00000000   $r2 0x00000000   $r3 0x00000000  $r4 0x00000000   $r5 0x00000000   $r6 0x00000000   $r7 0x00000000  $r8 0x00000000   $r9 0x00000000   $r10 0x00000000  $r11 0x00000000  $r12 0x00000000  $sp 0xbefff7e0   $lr 0x00000000          $pc 0x00008054          $cpsr 0x00000010          0x8054 <_start> mov r0, pc     <- $pc          0x8058 <_start+4> mov r0, #ii 0x805c <_start+eight> add r1, r0, r0 0x8060 <_start+12> bkpt 0x0000 0x8064 andeq r1, r0, r1, asr #ten 0x8068 cmnvs r5, r0, lsl #two 0x806c tsteq r0, r2, ror #xviii 0x8070 andeq r0, r0, r11 0x8074 tsteq r8, r6, lsl #6

We can see that PC holds the accost (0x8054) of the next instruction (mov r0, pc) that will be executed. Now let'due south execute the side by side teaching after which R0 should hold the accost of PC (0x8054), correct?

                      $r0 0x0000805c                                $r1 0x00000000   $r2 0x00000000   $r3 0x00000000  $r4 0x00000000   $r5 0x00000000   $r6 0x00000000   $r7 0x00000000  $r8 0x00000000   $r9 0x00000000   $r10 0x00000000  $r11 0x00000000  $r12 0x00000000  $sp 0xbefff7e0   $lr 0x00000000          $pc 0x00008058          $cpsr 0x00000010          0x8058 <_start+4> mov r0, #2       <- $pc                      0x805c                    <_start+8> add r1, r0, r0 0x8060 <_start+12> bkpt 0x0000 0x8064 andeq r1, r0, r1, asr #x 0x8068 cmnvs r5, r0, lsl #2 0x806c tsteq r0, r2, ror #18 0x8070 andeq r0, r0, r11 0x8074 tsteq r8, r6, lsl #6 0x8078 adfcssp f0, f0, #4.0

…right? Wrong. Look at the address in R0. While we expected R0 to comprise the previously read PC value (0x8054) it instead holds the value which is two instructions ahead of the PC we previously read (0x805c). From this example you lot can encounter that when nosotros directly read PC it follows the definition that PC points to the next education; but when debugging, PC points two instructions ahead of the electric current PC value (0x8054 + viii = 0x805C). This is because older ARM processors always fetched ii instructions alee of the currently executed instructions. The reason ARM retains this definition is to ensure compatibility with earlier processors.